1. Field of the Invention
The present invention relates to a memory circuit, and more particularly to a memory circuit which is composed of a insulated gate field effect transistor (which will be hereinafter referred to as "IGFET" or "MISFET").
2. Description of the Prior Art
In a static RAM (Random Access Memory), a plurality of memory cell circuits are arranged in the form of a matrix, in which the plural memory cell circuits in an identical row have their respective selecting terminals connected commonly with one word line whereas the plural memory cell circuits in an identical column have their respective input and output terminals connected commonly with one digit line.
As a result, the row of the memory cell circuits connected with the word line is selected by feeding the output of an X decoder circuit to that particular word line.
The static RAM can be so constructed as to have its plural digit lines coupled to a common data line through switch means (or a column gate) which is controlled by the output of a Y decoder. Then, it is sufficient that a write circuit and a read out circuit are provided for the common data line. According to this system, the circuit construction can be simplified as compared with the case in which the write circuit and the read out circuit are provided for each of the digit line.
Among the plural memory cell circuits of the RAM, the memory cell circuit selected by the output of the X decoder circuit and the output of the Y decoder circuit is connected with the common data line through the digit line and the switch means. Thus, for the memory cell circuit selected, information is written through the common data line, or the information in the selected memory cell circuit is read out through the common data line.
In the memory circuit, moreover, peripheral circuits such as a decoder circuit or an input and output circuit require a somewhat higher minimum supply voltage limit than the memory cell circuit constituting the memory circuit. When the supply voltage is lowered, the peripheral circuits may malfunction so that the information held in the memory cell circuits is lost by erroneous control signals and/or data signals.
On the other hand, the access time of the memory circuit is restricted by the delay in the operation of data transfer means such as the switch means.